Modern computer systems typically have one or more internal buses by which data can be communicated among different devices within the computer systems. For example, in computer systems based around the Itanium 2 microprocessor available from Intel Corporation of Santa Clara, Calif. (and co-developed by Intel with the Hewlett-Packard Company of Palo Alto, Calif.), a front side bus (FSB) allows for communication among several such microprocessors and/or possibly other devices including, for example, memory devices or input/output devices.
As the speeds of computer processing devices have continued to increase, it has become increasingly difficult for the transmission rates along the buses used in conjunction with those processing devices to keep up with the operational speeds of the processing devices. Consequently, buses such as the FSB have increasingly become bottlenecks limiting the performance of the overall computer systems. With respect to at least some types of buses, including the FSB, competing design considerations limit the degree to which transmission rates along the buses can be improved.
For example, the signals transmitted along buses such as the FSB include two major groupings of signals, source synchronous (SS) signals and common clock (CC) signals. Although transmitted along the same bus, SS signals tend to be more sensitive to electrical noise than CC signals and also tend to suffer more from reflections generated along the signal trace(s) than CC signals. Such concerns relating to the SS signals are typically mitigated by driving the signals on the FSB at a relatively low slew rate. Yet, because the signals on the FSB are driven at a low slew rate, higher data transmission rates that might otherwise be attainable through the use of CC signals driven at higher slew rates are precluded.
For at least the above reasons, it would be advantageous if an improved method and system for communicating signals in relation to computer systems could be developed. More particularly, it would be advantageous if an improved method and system could be achieved for communicating signals on buses (internal or otherwise) between computer components such as processors in a higher speed manner.